RTL, gate-level or mixed - Auspy Partition System II (APSII) partitions designs in RTL or gate-level into multiple-FPGA implementations. The RTL portion of the design will be synthesized modularly with the encapsulated commercial FPGA synthesis tools from Mentor Graphics, Synopsys, Synplicity or Xilinx. The parallel synthesis option reduces the run time dramatically for big designs. There is almost no limit in the design complexity to be processed with this hierarchical approach. The original design hierarchy boundaries will be kept unchanged for the best partition result. After partition, either RTL or gate-level could be exported for each FPGA. The hierarchical RTL code of each FPGA include the original RTL sources of un-partitioned modules and the structural codes of partitioned modules which are most likely at the higher level of the design hierarchy with its complexity exceeding a single FPGA.
Minimum number of FPGA's or lowest pin multiplexing - The automatic partition could target either unlimited or the fixed number of FPGA devices. In the case of unlimited FPGA devices, automatic partition searches for the solution with the minimum number of FPGA's. In the case of the fixed number of FPGA devices, automatic partition searches for the solution with the lowest pin multiplexing.
Advanced automatic partition - The proprietary automatic partition algorithm produces high-quality solution with the minimum inter- FPGA connections and timing-correct high-speed prototypes. The hierarchical approach makes possible to partition very large design. Manual grouping and limits on the target prototyping platform are observed. Domain-driven feature produces the partition solution with the low-skew clock distribution. The signal-flow clustering algorithm not only minimizes the required FPGA pins, but also minimizes the combinatorial paths through FPGA's for high- speed prototypes. Logic may be duplicated in the course of optimization. The detailed reports on the clock distribution, pin multiplexing and timing characteristics of inter-FPGA signals are presented after the completion of the partition.
Optional manual partition - In APSII, partition could be done manually, semi-automatically or automatically at the user's choice. The user could manually partition portion of the design to meet the special requirements and let the automatic partition finishes the rest. Variety of manual groups accommodates different needs. A manual group is a collection of instances or primary I/O's to be associated with any FPGA or one designated FPGA. A manual group marked as "shared" will be duplicated in all FPGA's containing logic driven by this group. The "shared" group is sometimes used to duplicate the clock structure to generate clocks locally if so required. The grouping could be specified at any hierarchy level without flattening the design. The impact analysis and hierarchical browser assists the user to make informed decision on the manual partition.
Low-skew clock distribution - The clock skew management is critical if the design has a large number of clocks or internally generated clocks. FPGA's have limited number of global buffers to distribute clocks and the prototyping platforms usually only support limited number of global clocks. When the number of design clocks exceeds the FPGA limit, the number of clock domains partitioned into any single FPGA will be limited by the domain-driven feature in APSII so every clock could be driven by the global buffer. The clock skew reaching each FPGA on the target prototyping platform is also carefully managed with the domain-driven feature. APSII supports a few schemes for the clock distribution. One scheme is to isolate the clock generation by creating the loop-back for the clock on the generation FPGA. Many prototyping platforms supports this loop-back feature on their global lines. If the design has more clocks than the global lines, another scheme could be adopted for smaller clocks by isolating the clock generation from its driving clock domain. The clock is then distributed from the clock-generation FPGA to the destination FPGA's with low-skew traces on the target prototyping platform. Some clock generation modules such as PLL's or DCM's could be duplicated in every FPGA to reproduce their derived clocks locally. With the domain-driven feature, APSII supports all the above clock distribution schemes for a single design if so required. Also, automatic partition will group the same-domain circuit into a single FPGA if possible to reduce the needs to distribute clocks on the target prototyping platform and bring up the prototyping performance.
Gated-clock conversion - APSII converts gated clocks generated from qualified combinatorial gates. The conversion re-connects the source clock to drive directly into the clock pins of storage instances and moves the qualified combinatorial gates to drive the enable pins of the storage instances. The qualified conversions are automatically identified and presented to the user for approval. The conversions could be cascaded in multiple stages. The conversions could also cross the design hierarchy boundaries.
Timing-correct pin multiplexing - The pin multiplexing relieves the pin requirements on FPGA's. The user has the option to use either the asynchronous or synchronous implementation of pin multiplexing. The asynchronous pin multiplexing uses a single system fast clock to drive the pin multiplexing logic. Signals with the same source and destination FPGA's could be grouped to share the same board trace through the pin multiplexing logic. After partition, APSII will instantiate the pin multiplexing logic including senders, receivers and control modules in every FPGA's according to the list of pin multiplexing signals reported by the automatic partition and approved by the user. The pin multiplexing IP's of the sender, receiver and controller are provided by the third party, not shipped by Auspy. The user can prepare his own IP's or use the certified IP's from Auspy's OEM partners. APSII also supports synchronous pin multiplexing. With the domain-driven technology, APSII is capable of implementing the pin multiplexing based on the clock domain. More rigid than the asynchronous scheme, the group of signals has to be in the same clock domain, in addition to the same source and destination FPGA's, to be pin-multiplexed. The combinatorial pass-through's could be excluded for pin multiplexing if so desired. Automatic partition accurately tracks the FPGA pin count affected by the pin multiplexing and finds the solution with the lowest pin multiplexing.
Fixed, incremental or fast probes - APSII brings probes out to the unused FPGA pins. Fixed probes are specified before partition and automatic partition will reserve the required FPGA pins accordingly. Incremental probes are specified after partition and will be brought out to the unused FPGA pins without re-partition the design. However, the time consuming FPGA place-and-route needs to be run to finalize these probes. FPGA place-and-route software offers the incremental capability to implement probes for a special class of signals. APSII will present this special group of probe candidates to the user to be selected as the fast probes which could be implemented with the fast incremental FPGA place-and-route.
Supported FPGA families - Altera Stratix, StratixII and Xilinx Virtex, VirtexII, Virtex4 and Virtex5.
Superior automatic partition in FPGA pin usage, area and timing. Works on RTL, gate-level or mixed. Integrated tightly with major commercial FPGA synthesis tools. Handles very large designs with the hierarchical approach. Handles complex clocks with the domain-driven partition. Automatically creates loop-back configurations for global clocks. Automatically replicates clock modules such as PLL's or DCM's. Automatically converts gated clocks across hierarchies. Timing-correct pin multiplexing with the domain-driven partition. Logic replication to reduce FPGA pins and bring up prototyping performance. Global logic trimming optimizes logic across hierarchies. Detailed reports on the clock distribution and timing characteristics of inter-FPGA signals. Supports fixed, incremental and fast probes. No design modifications needed for prototyping. Inserts custom co-simulation and/or debugging IP's. Parallel synthesis. Parallel FPGA place-and-route.
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