Auspy Development Inc. is an EDA company specializing in the multiple-FPGA partition. The next-generation partition solution automates the implementation of ASIC prototypes with the more affordable price. Two products are available :

• Auspy Partition System II (APSII) partitions designs in RTL or gate-level into multiple FPGA implementations. The proprietary automatic partition algorithm produces high-quality solution with the minimum inter-FPGA connections and timing-correct high-speed prototypes. The hierarchical approach allows the tool to manage very large design. One customer has partitioned a 40 million gate design in hours automatically by the tool. The relationship between the original and partitioned design is hierarchically established for very easy cross reference. Embedded timing engine empowers the tool to optimize the system timing by converting gated clocks, minimizing combinatorial paths through FPGA's, limiting number of clock domains partitioned into each FPGA to ensure that every clock is driven by a global buffer, isolating clock generation to balance the system skew reaching every FPGA, replicating FPGA clock modules such as PLL's or DCM's, and multiplexing pins within the same clock domain. Variety of constraints, such as manual grouping, hard macros or target system interface, are observed to achieve the working partition. With APSII, you no longer need to manually partition every module in the design, work diligently within the limits of the target prototyping platform, modify the design for the clock distribution or degrade the prototyping performance due to the excessive pin multiplexing. APSII saves weeks or months in your tight prototyping schedule. 
• Auspy Custom Emulator Compiler (ACE Compiler) maps designs in RTL or gate-level onto the custom-built or commercial prototyping platforms. ACE is equipped with the same partition engine as APSII. In addition, ACE performs the automatic system routing to connect inter-FPGA signals through board traces, fix FPGA pin locations and assign system I/O's to connector pins on the target prototyping platform. In addition to FPGA, ACE also faithfully models programmable switches, connectors, cables, daughter boards and clock distribution scheme on the target prototyping platform. The proprietary routing algorithm minimizes signal delays while searching paths through FPGA's, programmable switches and connected cables. Cables could be manually or automatically connected between connectors to provide extra traces for inter-FPGA connections. ACE is capable of overcoming the prototyping platform limits such as the distribution of local clocks or the implementation of the bi-directional buses in shortage of global wires. ACE supports the dynamic connectivity reconfiguration of the target prototyping platform with cables or connection plates without re-partitioning the design. Variety of constraints such as manual routing assignment, target system interface or cable connections are observed to produce the working mapping of the design onto the target prototyping platform. The tool is designed to be customizable to bring out the best performance of customer-built or commercial prototyping platforms. With ACE, the user no longer needs to manually partition every module in the design, work diligently within the limits of the target prototyping platform, modify the design for the clock distribution, degrade the prototyping performance due to the excessive pin multiplexing or manually complete hundreds or thousands of connections on the target prototyping platform. ACE saves you weeks or months in your tight prototyping schedule to map your design efficiently onto your custom-built or commercial prototyping platform. Download datasheet now.

Both tools are tightly integrated with the commercial FPGA synthesis tools from Mentor Graphics, Synopsys, Synplicity and Xilinx. Both tools are tightly integrated with FPGA place-and-route tools from Altera and Xilinx. The high-complexity FPGA families supported by the tools include Xilinx Virtex, VirtexII, Virtex4 and Virtex5, Altera Stratix and StratixII.

Auspy has been licensing its products to commercial prototyping platform vendors. More than 100 copies of software has been sold worldwide through these OEM partners. Auspy also supports the custom-built prototyping platforms directly together with its distributors, Maojet of Taiwan, ED&C of Korea and Bar-Nova of Israel. Auspy is very proud of its commitment to customers and partners. The past record shows that we have resolved most support issues within 24 hours. 

Auspy is open to the customization of its core technology for any innovative idea in the related fields such as the floor planning.

Auspy Development Inc. (The Partition Company)

10430 South De Anza Boulevard Suite 275 Cupertino, CA 95014 United States

Copyright (c) 2006 Auspy Development Inc. All rights reserved